Re: [Intel-gfx] [PATCH] drm/i915: Fix CHICKEN_TRANS register offset

2018-06-27 Thread Rodrigo Vivi
On Wed, Jun 27, 2018 at 04:14:01PM -0700, José Roberto de Souza wrote: > This registers offsets is not sequential for transcoder D and EDP so > for EDP transcoder it was writing to 0x420d0 that do not map to > any register in spec. > > CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to a

[Intel-gfx] [PATCH] drm/i915: Fix CHICKEN_TRANS register offset

2018-06-27 Thread José Roberto de Souza
This registers offsets is not sequential for transcoder D and EDP so for EDP transcoder it was writing to 0x420d0 that do not map to any register in spec. CHICKEN_TRANS is used in PSR2 and intel_enable_ddi_hdmi() to apply WA #1143 but I'm not aware of any open issue cause by this offset error. Sp