On 2010.11.04 13:50:24 +0800, Zhenyu Wang wrote:
On 2010.11.04 02:23:46 +, Chris Wilson wrote:
On Tue, 2 Nov 2010 14:24:22 +0800, Zhenyu Wang zhen...@linux.intel.com
wrote:
I don't think transcoder bpc setting should matter, but sorry that I'm
short
of time to track down which
On Tue, 2 Nov 2010 14:24:22 +0800, Zhenyu Wang zhen...@linux.intel.com wrote:
I don't think transcoder bpc setting should matter, but sorry that I'm short
of time to track down which one extra read made the difference, my sandybridge
laptop normally refuse to boot on first time.. ;)
The code
On 2010.10.29 09:52:31 +0100, Chris Wilson wrote:
On Fri, 29 Oct 2010 10:34:51 +0800, Zhenyu Wang zhen...@linux.intel.com
wrote:
On 2010.10.28 10:50:04 +0100, Chris Wilson wrote:
I've shrunk the patch to just the FDI portion, pushed to staging for
review.
Current drm-intel-staging
On Fri, 29 Oct 2010 10:34:51 +0800, Zhenyu Wang zhen...@linux.intel.com wrote:
On 2010.10.28 10:50:04 +0100, Chris Wilson wrote:
I've shrunk the patch to just the FDI portion, pushed to staging for
review.
Current drm-intel-staging still fails unfortunately..
I'm very interested to know
We should enable FDI normal training on Sandybridge/CPT system
as well. Also restore back some original register posting read
that got removed. LVDS/VGA/HDMI seems back to life but DP still
fails.
Signed-off-by: Zhenyu Wang zhen...@linux.intel.com
---
drivers/gpu/drm/i915/i915_drv.h |1
On Thu, 28 Oct 2010 16:38:08 +0800, Zhenyu Wang zhen...@linux.intel.com wrote:
We should enable FDI normal training on Sandybridge/CPT system
as well. Also restore back some original register posting read
that got removed. LVDS/VGA/HDMI seems back to life but DP still
fails.
The POSTING_READs
On 2010.10.28 10:50:04 +0100, Chris Wilson wrote:
The POSTING_READs you added are no-ops since they are all followed by a
read. The transconf should have the bpc in the register at this point or
else we should have bugged much earlier. The break-exec-wait condition is
still documented for
