We have problems of tgl not seeing a valid pte entry
when iommu is enabled. Add heavy handed flushing
of entry modification by flushing the cpu, cacheline
and then wcb. This forces the pte out to main memory
past this point regarless of promises of coherency.
This is an evolution of an experimenta
Quoting Mika Kuoppala (2020-05-11 17:08:03)
> We have problems of tgl not seeing a valid pte entry
> when iommu is enabled. Add heavy handed flushing
> of entry modification by flushing the cpu, cacheline
> and then wcb. This forces the pte out to main memory
> past this point regarless of promises
Quoting Chris Wilson (2020-05-11 17:13:52)
> Quoting Mika Kuoppala (2020-05-11 17:08:03)
> > We have problems of tgl not seeing a valid pte entry
> > when iommu is enabled. Add heavy handed flushing
> > of entry modification by flushing the cpu, cacheline
> > and then wcb. This forces the pte out t
