> -Original Message-
> From: Lisovskiy, Stanislav
> Sent: Monday, January 30, 2023 5:59 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Lisovskiy, Stanislav ; Saarinen, Jani
> ; Srivatsa, Anusha
> Subject: [PATCH] drm/i915: Implement workaround for CDCLK PLL
> disable/enable
>
> It was
It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.
v2: - Added WA number comment(R
On Tue, Jan 24, 2023 at 09:42:24AM +0200, Lisovskiy, Stanislav wrote:
> On Mon, Jan 23, 2023 at 02:52:37PM -0500, Rodrigo Vivi wrote:
> > On Mon, Jan 23, 2023 at 03:16:11PM +0200, Stanislav Lisovskiy wrote:
> > > It was reported that we might get a hung and loss of register access in
> > > some cas
On Mon, Jan 23, 2023 at 02:52:37PM -0500, Rodrigo Vivi wrote:
> On Mon, Jan 23, 2023 at 03:16:11PM +0200, Stanislav Lisovskiy wrote:
> > It was reported that we might get a hung and loss of register access in
> > some cases when CDCLK PLL is disabled and then enabled, while squashing
> > is enabled
On Mon, Jan 23, 2023 at 03:16:11PM +0200, Stanislav Lisovskiy wrote:
> It was reported that we might get a hung and loss of register access in
> some cases when CDCLK PLL is disabled and then enabled, while squashing
> is enabled.
> As a workaround it was proposed by HW team that SW should disable
It was reported that we might get a hung and loss of register access in
some cases when CDCLK PLL is disabled and then enabled, while squashing
is enabled.
As a workaround it was proposed by HW team that SW should disable squashing
when CDCLK PLL is being reenabled.
Signed-off-by: Stanislav Lisovs
