On Wed, Mar 11, 2015 at 10:30:13AM +, Chris Wilson wrote:
On Wed, Mar 11, 2015 at 11:13:59AM +0100, Daniel Vetter wrote:
Also do you have microbenchmark numbers for something midly ridiculous
like a loop of very short batches (enough ofc to cause a bit of delay) and
immediately stalling
On Tue, Mar 10, 2015 at 04:14:14PM +, Chris Wilson wrote:
On Tue, Mar 10, 2015 at 04:06:19PM +, Chris Wilson wrote:
@@ -1235,12 +1257,20 @@ int __i915_wait_request(struct drm_i915_gem_request
*req,
if (ring-id == RCS INTEL_INFO(dev)-gen = 6)
On Wed, Mar 11, 2015 at 11:13:59AM +0100, Daniel Vetter wrote:
On Tue, Mar 10, 2015 at 04:14:14PM +, Chris Wilson wrote:
On Tue, Mar 10, 2015 at 04:06:19PM +, Chris Wilson wrote:
@@ -1235,12 +1257,20 @@ int __i915_wait_request(struct
drm_i915_gem_request *req,
if (ring-id ==
Tested-By: PRC QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 5928
-Summary-
Platform Delta drm-intel-nightly Series Applied
PNV -1 282/282
On Tue, Mar 10, 2015 at 04:06:19PM +, Chris Wilson wrote:
@@ -1235,12 +1257,20 @@ int __i915_wait_request(struct drm_i915_gem_request
*req,
if (ring-id == RCS INTEL_INFO(dev)-gen = 6)
gen6_rps_boost(dev_priv, file_priv);
- if (!irq_test_in_progress
This provides a nice boost to mesa in swap bound scenarios (as mesa
throttles itself to the previous frame and given the scenario that will
complete shortly). It will also provide a good boost to systems running
with semaphores disabled and so frequently waiting on the GPU as it
switches rings.
