Dual link Z-inversion overlap field is present
in MIPI_CTRL register unlike the older platforms,
hence setting the same in this patch.

Signed-off-by: Deepak M <m.dee...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |  2 ++
 drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bdc7b35..7a79dd1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8350,6 +8350,8 @@ enum {
 #define _MIPIA_CTRL                    (dev_priv->mipi_mmio_base + 0xb104)
 #define _MIPIC_CTRL                    (dev_priv->mipi_mmio_base + 0xb904)
 #define MIPI_CTRL(port)                        _MMIO_MIPI(port, _MIPIA_CTRL, 
_MIPIC_CTRL)
+#define  BXT_PIXEL_OVERLAP_CNT_MASK                    (0xf << 10)
+#define  BXT_PIXEL_OVERLAP_CNT_SHIFT                   10
 #define  ESCAPE_CLOCK_DIVIDER_SHIFT                    5 /* A only */
 #define  ESCAPE_CLOCK_DIVIDER_MASK                     (3 << 5)
 #define  ESCAPE_CLOCK_DIVIDER_1                                (0 << 5)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 4e0d025..b1a4675 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -455,12 +455,21 @@ static void intel_dsi_port_enable(struct intel_encoder 
*encoder)
 
        if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
                u32 temp;
-
-               temp = I915_READ(VLV_CHICKEN_3);
-               temp &= ~PIXEL_OVERLAP_CNT_MASK |
+               if (IS_BROXTON(dev_priv)) {
+                       for_each_dsi_port(port, intel_dsi->ports) {
+                               temp = I915_READ(MIPI_CTRL(port));
+                               temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
+                                       intel_dsi->pixel_overlap <<
+                                       BXT_PIXEL_OVERLAP_CNT_SHIFT;
+                               I915_WRITE(MIPI_CTRL(port), temp);
+                       }
+               } else {
+                       temp = I915_READ(VLV_CHICKEN_3);
+                       temp &= ~PIXEL_OVERLAP_CNT_MASK |
                                        intel_dsi->pixel_overlap <<
                                        PIXEL_OVERLAP_CNT_SHIFT;
-               I915_WRITE(VLV_CHICKEN_3, temp);
+                       I915_WRITE(VLV_CHICKEN_3, temp);
+               }
        }
 
        for_each_dsi_port(port, intel_dsi->ports) {
-- 
1.9.1

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