Re: [Intel-gfx] [PATCH] drm/i915: Use the correct maximum in skl_compute_plane_wm

2018-01-30 Thread Ville Syrjälä
On Tue, Jan 30, 2018 at 02:54:11PM +0100, Maarten Lankhorst wrote: > According to bspec, result_lines > 31 is only a maximum for latency > level 1 through 7, so correctly apply the check there. The register still has only 5 bits for the line watermark. However the spec says "Hardware ignores the l

[Intel-gfx] [PATCH] drm/i915: Use the correct maximum in skl_compute_plane_wm

2018-01-30 Thread Maarten Lankhorst
According to bspec, result_lines > 31 is only a maximum for latency level 1 through 7, so correctly apply the check there. This is required to make NV12 work. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a