On 2010.10.13 09:00:37 -0700, Jesse Barnes wrote:
>
> So this gets the display working again with current bits?
>
No, these two are the fixes coming out during my bisect, as
it looks we have multiple regression commits...
--
Open Source Technology Center, Intel ltd.
$gpg --keyserver wwwkeys.p
On Wed, 13 Oct 2010 09:00:37 -0700, Jesse Barnes
wrote:
> On Wed, 13 Oct 2010 16:40:11 +0800
> Zhenyu Wang wrote:
>
> > FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge.
The VPN ate the response that I've applied both of these, with a tweak to
this patch to move the if
On Wed, 13 Oct 2010 16:40:11 +0800
Zhenyu Wang wrote:
> FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge.
>
> Signed-off-by: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/intel_display.c |5 -
> 1 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/drive
FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge.
Signed-off-by: Zhenyu Wang
---
drivers/gpu/drm/i915/intel_display.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
