Ander Conselvan de Oliveira (12):
drm/i915/glk: Introduce Geminilake platform definition
drm/i915/glk: Add Geminilake PCI IDs
drm/i915/glk: Add a IS_GEN9_LP() macro
drm/i915/glk: Reuse broxton code for geminilake
drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too
drm/i915/glk: Add power wells for Geminilake
drm/i915/glk: Implement Geminilake DDI init sequence
drm/i915/glk: Set DDC delay range 2 in PLL enable sequence
drm/i915/glk: Reuse broxton's cdclk code for GLK
drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake
drm/i915/glk: Implement core display init/uninit sequence for
geminilake
drm/i915/glk: Configure number of sprite planes properly
Madhav Chauhan (1):
drm/i915/glk: Update Port PLL enable sequence for Geminilkae
Rodrigo Vivi (2):
drm/i915: Create a common GEN9_LP_FEATURE.
drm/i915/glk: Force DDI initialization.
drivers/gpu/drm/i915/i915_debugfs.c | 12 +--
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c | 10 +-
drivers/gpu/drm/i915/i915_pci.c | 55 ++++++-----
drivers/gpu/drm/i915/i915_reg.h | 44 +++++++--
drivers/gpu/drm/i915/intel_bios.c | 2 +-
drivers/gpu/drm/i915/intel_ddi.c | 18 ++--
drivers/gpu/drm/i915/intel_device_info.c | 5 +-
drivers/gpu/drm/i915/intel_display.c | 89 ++++++++++++++---
drivers/gpu/drm/i915/intel_dp.c | 20 ++--
drivers/gpu/drm/i915/intel_dpio_phy.c | 114 ++++++++++++++++++---
drivers/gpu/drm/i915/intel_dpll_mgr.c | 32 +++++-
drivers/gpu/drm/i915/intel_dsi.c | 28 +++---
drivers/gpu/drm/i915/intel_dsi_pll.c | 12 +--
drivers/gpu/drm/i915/intel_hdmi.c | 6 +-
drivers/gpu/drm/i915/intel_i2c.c | 4 +-
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_panel.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 6 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 163 +++++++++++++++++++++++++++++--
include/drm/i915_pciids.h | 4 +
22 files changed, 508 insertions(+), 138 deletions(-)
--
2.5.5
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