[Intel-gfx] [PATCH 017/190] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+

2016-01-11 Thread Chris Wilson
In order to ensure seqno/irq coherency, we current read a ring register. We are not sure quite how it works, only that is does. Experiments show that e.g. doing a clflush(seqno) instead is not sufficient, but we can remove the forcewake dance from the mmio access. v2: Baytrail wants a clflush too.

Re: [Intel-gfx] [PATCH 017/190] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+

2016-03-23 Thread David Weinehall
On Mon, Jan 11, 2016 at 09:16:28AM +, Chris Wilson wrote: > In order to ensure seqno/irq coherency, we current read a ring register. currently > We are not sure quite how it works, only that is does. Experiments show > that e.g. doing a clflush(seqno) instead is not sufficient, but we can > r

Re: [Intel-gfx] [PATCH 017/190] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+

2016-01-11 Thread Dave Gordon
On 11/01/16 09:16, Chris Wilson wrote: In order to ensure seqno/irq coherency, we current read a ring register. We are not sure quite how it works, only that is does. Experiments show that e.g. doing a clflush(seqno) instead is not sufficient, but we can remove the forcewake dance from the mmio a

Re: [Intel-gfx] [PATCH 017/190] drm/i915: Remove forcewake dance from seqno/irq barrier on legacy gen6+

2016-01-21 Thread Mika Kuoppala
Dave Gordon writes: > On 11/01/16 09:16, Chris Wilson wrote: >> In order to ensure seqno/irq coherency, we current read a ring register. >> We are not sure quite how it works, only that is does. Experiments show >> that e.g. doing a clflush(seqno) instead is not sufficient, but we can >> remove t