Re: [Intel-gfx] [PATCH 02/14] drm/i915: improve SERR_INT clearing for fifo underrun reporting

2013-07-08 Thread Paulo Zanoni
2013/7/4 Daniel Vetter : > The current code won't report any fifo underruns on cpt if just one > pipe has fifo underrun reporting disabled. We can't enable the > interrupts, but we can still check the per-transcoder bits and so > report the underrun delayed if: > - We always clear the transcoder's

[Intel-gfx] [PATCH 02/14] drm/i915: improve SERR_INT clearing for fifo underrun reporting

2013-07-04 Thread Daniel Vetter
The current code won't report any fifo underruns on cpt if just one pipe has fifo underrun reporting disabled. We can't enable the interrupts, but we can still check the per-transcoder bits and so report the underrun delayed if: - We always clear the transcoder's bit (and none of the other bits)