As per B.Spces DC5 and DC6 not allowed when DC3CO is enabled.
and DC3CO should be enabled only during VIDEO playback.
Which essentially means both can DC5 and DC3CO can not be
enabled at same time.
This patch makes DC3CO and DC5 mutual exclusive.
Cc: jani.nik...@intel.com
Cc: imre.d...@intel.com
Cc: rodrigo.v...@intel.com
Cc: animesh.ma...@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gu...@intel.com>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b29761b4f55e..3f87e9bb9f94 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1233,6 +1233,10 @@ static void gen9_dc_off_power_well_enable(struct
drm_i915_private *dev_priv,
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /* DC3CO and DC5/6 are mutually exclusive */
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_allow_dc3co(dev_priv);
+
dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -1257,6 +1261,10 @@ static void gen9_dc_off_power_well_disable(struct
drm_i915_private *dev_priv,
if (!dev_priv->csr.dmc_payload)
return;
+ /* DC3CO and DC5/6 are mutually exclusive */
+ if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+ tgl_disallow_dc3co(dev_priv);
+
if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
skl_enable_dc6(dev_priv);
else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
--
2.21.0
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