subject:"\[Intel\-gfx\] \[PATCH 04\/27\] drm\/i915\/icl\: Icelake interrupt register addresses and bits"

Re: [Intel-gfx] [PATCH 04/27] drm/i915/icl: Icelake interrupt register addresses and bits

2018-01-10 Thread Paulo Zanoni

Em Ter, 2018-01-09 às 21:23 -0200, Paulo Zanoni escreveu: > From: Tvrtko Ursulin > > MMIO addresses and register definition for the new interrupt > registers in Gen11. > > v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter) > v3: Adjust VCS and VECS.

[Intel-gfx] [PATCH 04/27] drm/i915/icl: Icelake interrupt register addresses and bits

2018-01-09 Thread Paulo Zanoni

From: Tvrtko Ursulin MMIO addresses and register definition for the new interrupt registers in Gen11. v2: Removed spelt out VCS and VECS bit definitions. (Daniel Vetter) v3: Adjust VCS and VECS. (Daniele Ceraolo Spurio) v4: Bikeshedding (Paulo). Cc: Ceraolo Spurio,