Re: [Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8

2014-07-07 Thread Daniel Vetter
On Mon, Jun 30, 2014 at 09:53:39AM -0700, Rodrigo Vivi wrote: > Ipehr just carries Dword 0 and on Gen 8, offsets are located > on Dword 2 and 3 of MI_SEMAPHORE_WAIT. > > This implementation was based on Ben's work and on Ville's suggestion for Ben > > Cc: Ville Syrjälä > Cc: Ben Widawsky > Sign

Re: [Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8

2014-06-30 Thread Ben Widawsky
On Mon, Jun 30, 2014 at 09:53:39AM -0700, Rodrigo Vivi wrote: > Ipehr just carries Dword 0 and on Gen 8, offsets are located > on Dword 2 and 3 of MI_SEMAPHORE_WAIT. > > This implementation was based on Ben's work and on Ville's suggestion for Ben > > Cc: Ville Syrjälä > Cc: Ben Widawsky > Sign

[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8

2014-06-30 Thread Rodrigo Vivi
Ipehr just carries Dword 0 and on Gen 8, offsets are located on Dword 2 and 3 of MI_SEMAPHORE_WAIT. This implementation was based on Ben's work and on Ville's suggestion for Ben Cc: Ville Syrjälä Cc: Ben Widawsky Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_irq.c | 42 +++

[Intel-gfx] [PATCH 05/10] drm/i915: Implement MI decode for gen8

2014-05-07 Thread Ben Widawsky
From: Ben Widawsky This is needed to implement ipehr_is_semaphore_wait Signed-off-by: Ben Widawsky --- drivers/gpu/drm/i915/i915_irq.c | 11 +-- 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 2d76183