>To: Navare, Manasi D
> > >Cc: Srivatsa, Anusha ; Nikula, Jani
> > >; intel-gfx@lists.freedesktop.org
> > >Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
> > >
> > >On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
freedesktop.org
> >Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
> >
> >On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
> >> On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> >> > From: "Srivatsa, A
>-Original Message-
>From: Vivi, Rodrigo
>Sent: Wednesday, July 18, 2018 1:54 PM
>To: Navare, Manasi D
>Cc: Srivatsa, Anusha ; Nikula, Jani
>; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters
>
>On
On Wed, Jul 18, 2018 at 11:53:54AM -0700, Manasi Navare wrote:
> On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> > From: "Srivatsa, Anusha"
> >
> > The Picture Parameter Set metadata for DSC has to be sent
> > to the panel through secondary data packets. Add the error
> > corre
On Tue, Jul 17, 2018 at 02:10:58PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha"
>
> The Picture Parameter Set metadata for DSC has to be sent
> to the panel through secondary data packets. Add the error
> correction registers, data registers and control registers
> for the same.
>
>
From: "Srivatsa, Anusha"
The Picture Parameter Set metadata for DSC has to be sent
to the panel through secondary data packets. Add the error
correction registers, data registers and control registers
for the same.
The control registers for transcoders A and B are already
defined and will be re
