Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR
> > around cdclk changes to ADL-P
> >
> > On Thu, 2021-06-17 at 14:12 -0700, Anusha Srivatsa wrote:
> > > From: Gwan-gyeong Mun
> > >
> > > Only ADL-P platform requires a temporal disabling
> -Original Message-
> From: Souza, Jose
> Sent: Thursday, June 17, 2021 2:18 PM
> To: Mun, Gwan-gyeong ; Srivatsa, Anusha
> ; intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 1/5] drm/i915/display: Limit disabling PSR
> around cdclk changes to AD
On Thu, 2021-06-17 at 14:12 -0700, Anusha Srivatsa wrote:
> From: Gwan-gyeong Mun
>
> Only ADL-P platform requires a temporal disabling of PSR for changing the
> CDCLK PLL frequency with crawling. Changing the CDCLK PLL frequency on
> prior platforms of ADL-P or changing the CDCLK PLL frequency w
From: Gwan-gyeong Mun
Only ADL-P platform requires a temporal disabling of PSR for changing the
CDCLK PLL frequency with crawling. Changing the CDCLK PLL frequency on
prior platforms of ADL-P or changing the CDCLK PLL frequency without
crawling on ADL-P don't need to disable of PSR.
Bspec: 49207
