Re: [Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy

2021-10-29 Thread Souza, Jose
On Wed, 2021-10-06 at 23:49 +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > Prepare for per-lane drive settings by querying the desired vswing > level per-lane. > > Note that the code only does two loops, with each one writing the > levels for two TX lanes. The register offsets also look a

[Intel-gfx] [PATCH 10/16] drm/i915: Query the vswing levels per-lane for tgl dkl phy

2021-10-06 Thread Ville Syrjala
From: Ville Syrjälä Prepare for per-lane drive settings by querying the desired vswing level per-lane. Note that the code only does two loops, with each one writing the levels for two TX lanes. The register offsets also look a bit funny because each time through the loop we write to the exact sa