Like on hsw/bdw the pipe only starts running once the port/pch
transcoder combo is all enabled. Before that the vblank wait in the
primary plane enable function simply times out.
This is also really nice prep work for atomic modesets since now all
the plane enabling is at the very end and all
On Tue, Apr 15, 2014 at 06:41:23PM +0200, Daniel Vetter wrote:
Like on hsw/bdw the pipe only starts running once the port/pch
transcoder combo is all enabled. Before that the vblank wait in the
primary plane enable function simply times out.
This is also really nice prep work for atomic
On Tue, Apr 15, 2014 at 10:05 PM, Ville Syrjälä
ville.syrj...@linux.intel.com wrote:
This more or less duplicates what's in my watermark series already. Except
you have a few more bugs here. The intel_wait_for_vblank() should be after
the plane enabling since it's a hack to avoid the flip done
