Render modifications could not trigger PSR exit this WA fixes it.
BSpec: 21664
Signed-off-by: José Roberto de Souza <jose.so...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index abb37437ff5d..2608c7e47aca 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4137,6 +4137,7 @@ enum {
#define TGL_VRH_GATING_DIS REG_BIT(31)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
+#define BXT_DPFC_GATING_DIS (1 << 31)
#define BXT_GMBUS_GATING_DIS (1 << 14)
#define _CLKGATE_DIS_PSL_A 0x46520
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8375054ba27d..02184888d193 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -139,6 +139,10 @@ static void bxt_init_clock_gating(struct drm_i915_private
*dev_priv)
* application, using batch buffers or any other means.
*/
I915_WRITE(RM_TIMEOUT, MMIO_TIMEOUT_US(950));
+
+ /* WA 1130 */
+ I915_WRITE(GEN9_CLKGATE_DIS_4,
+ I915_READ(GEN9_CLKGATE_DIS_4) | BXT_DPFC_GATING_DIS);
}
static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -152,6 +156,10 @@ static void glk_init_clock_gating(struct drm_i915_private
*dev_priv)
*/
I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
PWM1_GATING_DIS | PWM2_GATING_DIS);
+
+ /* WA 1130 */
+ I915_WRITE(GEN9_CLKGATE_DIS_4,
+ I915_READ(GEN9_CLKGATE_DIS_4) | BXT_DPFC_GATING_DIS);
}
static void pnv_get_mem_freq(struct drm_i915_private *dev_priv)
--
2.26.0
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