Re: [Intel-gfx] [PATCH 2/4] drm/i915/icl: No need to ack intr through master control

2018-10-12 Thread Matthew Auld
On Tue, 2 Oct 2018 at 15:07, Mika Kuoppala wrote: > > All other master control register bits, except the enable, > are read only and they are level indications of the second > level interrupt status. Only touch enable bit and rectify > the comment. > > Cc: Chris Wilson > Cc: Dhinakaran Pandiyan

[Intel-gfx] [PATCH 2/4] drm/i915/icl: No need to ack intr through master control

2018-10-02 Thread Mika Kuoppala
All other master control register bits, except the enable, are read only and they are level indications of the second level interrupt status. Only touch enable bit and rectify the comment. Cc: Chris Wilson Cc: Dhinakaran Pandiyan Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_irq.c