On Wed, Dec 07, 2022 at 11:35:24PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 07, 2022 at 01:05:15PM -0800, Navare, Manasi wrote:
> > On Wed, Dec 07, 2022 at 05:10:54PM +0200, Ville Syrjälä wrote:
> > > On Mon, Dec 05, 2022 at 12:34:25PM -0800, Navare, Manasi wrote:
> > > > On Fri, Dec 02, 2022 at 0
On Wed, Dec 07, 2022 at 01:05:15PM -0800, Navare, Manasi wrote:
> On Wed, Dec 07, 2022 at 05:10:54PM +0200, Ville Syrjälä wrote:
> > On Mon, Dec 05, 2022 at 12:34:25PM -0800, Navare, Manasi wrote:
> > > On Fri, Dec 02, 2022 at 03:44:10PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> >
On Wed, Dec 07, 2022 at 05:10:54PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 05, 2022 at 12:34:25PM -0800, Navare, Manasi wrote:
> > On Fri, Dec 02, 2022 at 03:44:10PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > We are miscalculating both the guardband value, and the resulti
On Mon, Dec 05, 2022 at 12:34:25PM -0800, Navare, Manasi wrote:
> On Fri, Dec 02, 2022 at 03:44:10PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We are miscalculating both the guardband value, and the resulting
> > vblank exit length on adl+. This means that our start of vblank
>
On Fri, Dec 02, 2022 at 03:44:10PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We are miscalculating both the guardband value, and the resulting
> vblank exit length on adl+. This means that our start of vblank
> (double buffered register latch point) is incorrect, and we also
> think t
From: Ville Syrjälä
We are miscalculating both the guardband value, and the resulting
vblank exit length on adl+. This means that our start of vblank
(double buffered register latch point) is incorrect, and we also
think that it's not where it actually is (hence vblank evasion/etc.
may not work p
