My cache coherency checker for i8xx chipsets will make cache flushes stateful. Therefore add some locking around the only caller that had none. This is not a fast-path, anyway, so it won't hurt for the other chipsets.
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch> --- drivers/gpu/drm/i915/i915_gem.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index f04612f..04fe7f5 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -5234,7 +5234,10 @@ i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, if (ret) return -EFAULT; + mutex_lock(&dev->struct_mutex); drm_agp_chipset_flush(dev); + mutex_unlock(&dev->struct_mutex); + return 0; } -- 1.7.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx