> -Original Message-
> From: Deak, Imre
> Sent: Wednesday, October 26, 2022 5:27 PM
> To: Kahola, Mika
> Cc: intel-gfx@lists.freedesktop.org; Srivatsa, Anusha
> ; Roper, Matthew D
> ; Souza, Jose
> Subject: Re: [PATCH 20/20] drm/i915/mtl: Pin assignment for TypeC
>
> On Fri, Oct 14,
On Fri, Oct 14, 2022 at 03:47:40PM +0300, Mika Kahola wrote:
> From: Anusha Srivatsa
>
> Unlike previous platforms that used PORT_TX_DFLEXDPSP
> for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
> from which the max_lanes has to be calculated.
>
> Bspec: 50235, 65380
> Cc: Mika Kahola
>
From: Anusha Srivatsa
Unlike previous platforms that used PORT_TX_DFLEXDPSP
for max_lane calculation, MTL uses only PORT_TX_DFLEXPA1
from which the max_lanes has to be calculated.
Bspec: 50235, 65380
Cc: Mika Kahola
Cc: Imre Deak
Cc: Matt Roper
Signed-off-by: Anusha Srivatsa
Signed-off-by:
