On Fri, Dec 13, 2019 at 12:40:13PM -0800, Manasi Navare wrote:
> On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrjälä wrote:
> > On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> > > While clearing the Ports ync mode enable and master select bits
> > > we need to make sure that we
On Fri, Dec 13, 2019 at 10:06:37PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> > While clearing the Ports ync mode enable and master select bits
> > we need to make sure that we perform a RMW for disable else
> > it sets the other bits casuing unwa
On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> While clearing the Ports ync mode enable and master select bits
> we need to make sure that we perform a RMW for disable else
> it sets the other bits casuing unwanted sideeffects.
>
> Bugzilla: https://gitlab.freedesktop.org/drm/int
On Wed, Dec 11, 2019 at 01:14:25PM -0800, Manasi Navare wrote:
> While clearing the Ports ync mode enable and master select bits
> we need to make sure that we perform a RMW for disable else
> it sets the other bits casuing unwanted sideeffects.
>
> Bugzilla: https://gitlab.freedesktop.org/drm/int
While clearing the Ports ync mode enable and master select bits
we need to make sure that we perform a RMW for disable else
it sets the other bits casuing unwanted sideeffects.
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
Cc: Ville Syrjälä
Cc: Jani Nikula
Fixes: 51528afe7c5e ("drm
