[Intel-gfx] [PATCH 3/3] drm/i915/gtt: Setup phys pages for 3lvl pdps

2019-06-18 Thread Mika Kuoppala
If we setup backing phys page for 3lvl pdps, even they are not used, we lose 5 pages per ppgtt. Trading this memory on bsw, we gain more common code paths for all gen8+ directory manipulation. And those paths are now void of checks for page directory type, making the hot paths faster. Signed-off-

[Intel-gfx] [PATCH 3/3] drm/i915/gtt: Setup phys pages for 3lvl pdps

2019-07-04 Thread Mika Kuoppala
If we setup backing phys page for 3lvl pdps, even they are not used, we lose 5 pages per ppgtt. Trading this memory on bsw, we gain more common code paths for all gen8+ directory manipulation. And those paths are now void of checks for page directory type, making the hot paths faster. v2: don't s

Re: [Intel-gfx] [PATCH 3/3] drm/i915/gtt: Setup phys pages for 3lvl pdps

2019-06-18 Thread Chris Wilson
Quoting Mika Kuoppala (2019-06-18 17:17:31) > If we setup backing phys page for 3lvl pdps, even they even though they > are not used, we lose 5 pages per ppgtt. > > Trading this memory on bsw, we gain more common code paths for all > gen8+ directory m