On Mon, Nov 12, 2018 at 07:19:44PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 09, 2018 at 04:58:22PM +0200, Imre Deak wrote:
> > Even though PW#1 and the MISC_IO power wells are managed by the
> > DMC firmware (toggled dynamically if conditions allow it) from the
> > driver's POV they are always on
On Fri, Nov 09, 2018 at 04:58:22PM +0200, Imre Deak wrote:
> Even though PW#1 and the MISC_IO power wells are managed by the
> DMC firmware (toggled dynamically if conditions allow it) from the
> driver's POV they are always on if the display core is initialized
> (always restored by DMC to the
Even though PW#1 and the MISC_IO power wells are managed by the
DMC firmware (toggled dynamically if conditions allow it) from the
driver's POV they are always on if the display core is initialized
(always restored by DMC to the enabled state after exiting from DC5/6
for instance b/c of MMIO
