Re: [Intel-gfx] [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions

2014-03-05 Thread Daniel Vetter
On Wed, Mar 05, 2014 at 02:40:58PM +, Damien Lespiau wrote: > On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > We have two names for the same register CHICKEN_PIPESL_1 and > > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. > > >

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions

2014-03-05 Thread Damien Lespiau
On Wed, Mar 05, 2014 at 01:05:47PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > We have two names for the same register CHICKEN_PIPESL_1 and > HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. > > Also rename the FBCQ disable bit to resemble the name we've > given to a sim

[Intel-gfx] [PATCH 3/3] drm/i915: Unify CHICKEN_PIPESL_1 register definitions

2014-03-05 Thread ville . syrjala
From: Ville Syrjälä We have two names for the same register CHICKEN_PIPESL_1 and HSW_PIPE_SLICE_CHICKEN_1. Unify it to just one. Also rename the FBCQ disable bit to resemble the name we've given to a similar bit on earlier platforms. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_