Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support

2019-01-24 Thread Souza, Jose
On Tue, 2019-01-22 at 14:42 -0800, Dhinakaran Pandiyan wrote: > On Wed, 2019-01-16 at 15:43 -0800, José Roberto de Souza wrote: > > If the sink and source supports HBR3, TP4 should be used as link > > training pattern. > > For PSR2 there is no register to set and enable TP4 but according > > to >

Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support

2019-01-22 Thread Dhinakaran Pandiyan
On Wed, 2019-01-16 at 15:43 -0800, José Roberto de Souza wrote: > If the sink and source supports HBR3, TP4 should be used as link > training pattern. > For PSR2 there is no register to set and enable TP4 but according to > eDP spec TP3 is still a training pattern acceptable for HBR3 panels. >

Re: [Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support

2019-01-17 Thread Manasi Navare
On Wed, Jan 16, 2019 at 03:43:20PM -0800, José Roberto de Souza wrote: > If the sink and source supports HBR3, TP4 should be used as link > training pattern. > For PSR2 there is no register to set and enable TP4 but according to > eDP spec TP3 is still a training pattern acceptable for HBR3

[Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support

2019-01-16 Thread José Roberto de Souza
If the sink and source supports HBR3, TP4 should be used as link training pattern. For PSR2 there is no register to set and enable TP4 but according to eDP spec TP3 is still a training pattern acceptable for HBR3 panels. Cc: Manasi Navare Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de