So far in an attempt to make sure all power wells get disabled during
display uninitialization the driver removed any secondary request bits
(BIOS, KVMR, DEBUG) that were set for a given power well. The known
source for these requests was DMC's request on power well 1 and the misc
IO power well. Si
This patch makes sense and seems the right thing to do...
However removing the sanitize with I915_WRITE(*, val & ~mask);
doesn't give me very comfortable...
I've seem many power well timeouts on cnl due the lack of that sanitize...
I will try to save some time here and do some experiments with cn
On Thu, Jun 29, 2017 at 01:06:01PM -0700, Rodrigo Vivi wrote:
> This patch makes sense and seems the right thing to do...
>
> However removing the sanitize with I915_WRITE(*, val & ~mask);
> doesn't give me very comfortable...
>
> I've seem many power well timeouts on cnl due the lack of that san
yep, makes total sense and you were right... no timeout..
Reviewed-by: Rodrigo Vivi
On Fri, Jun 30, 2017 at 5:29 AM, Imre Deak wrote:
> On Thu, Jun 29, 2017 at 01:06:01PM -0700, Rodrigo Vivi wrote:
>> This patch makes sense and seems the right thing to do...
>>
>> However removing the sanitize
