Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-08 Thread Chris Wilson
On Tue, Dec 08, 2015 at 11:07:01PM +0200, Ville Syrjälä wrote: > On Tue, Dec 08, 2015 at 08:50:48PM +, Chris Wilson wrote: > > On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote: > > > On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote: > > > > Do some further clean up based

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-08 Thread Ville Syrjälä
On Tue, Dec 08, 2015 at 08:50:48PM +, Chris Wilson wrote: > On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote: > > On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote: > > > Do some further clean up based on the initial review of > > > drm/i915: Separate cherryview from vall

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-08 Thread Chris Wilson
On Tue, Dec 08, 2015 at 07:45:50PM +0200, Ville Syrjälä wrote: > On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote: > > Do some further clean up based on the initial review of > > drm/i915: Separate cherryview from valleyview. > > > > In this case, in i915_gem_alloc_context_obj() only ca

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-08 Thread Ville Syrjälä
On Tue, Dec 08, 2015 at 09:38:52AM -0800, Wayne Boyer wrote: > Do some further clean up based on the initial review of > drm/i915: Separate cherryview from valleyview. > > In this case, in i915_gem_alloc_context_obj() only call > i915_gem_object_set_cache_level() for Ivy Bridge devices > since lat

[Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-08 Thread Wayne Boyer
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case, in i915_gem_alloc_context_obj() only call i915_gem_object_set_cache_level() for Ivy Bridge devices since later platforms don't have L3 control bits in the PTE. v2: Expand comment t

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-08 Thread Ville Syrjälä
On Mon, Dec 07, 2015 at 10:26:15PM +, Boyer, Wayne wrote: > On 12/7/15, 11:56 AM, "Deak, Imre" wrote: > > > >On Mon, 2015-12-07 at 21:28 +0200, Ville Syrjälä wrote: > >> On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote: > >> > Do some further clean up based on the initial review o

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-07 Thread Boyer, Wayne
On 12/7/15, 11:56 AM, "Deak, Imre" wrote: >On Mon, 2015-12-07 at 21:28 +0200, Ville Syrjälä wrote: >> On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote: >> > Do some further clean up based on the initial review of >> > drm/i915: Separate cherryview from valleyview. >> > >> > In this c

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-07 Thread Imre Deak
On Mon, 2015-12-07 at 21:28 +0200, Ville Syrjälä wrote: > On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote: > > Do some further clean up based on the initial review of > > drm/i915: Separate cherryview from valleyview. > > > > In this case, in i915_gem_alloc_context_obj() only call > >

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-07 Thread Ville Syrjälä
On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote: > Do some further clean up based on the initial review of > drm/i915: Separate cherryview from valleyview. > > In this case, in i915_gem_alloc_context_obj() only call > i915_gem_object_set_cache_level() for Ivy Bridge devices > since lat

[Intel-gfx] [PATCH 4/5] drm/i915: Only set gem object L3 cache level for IVB devices

2015-12-07 Thread Wayne Boyer
Do some further clean up based on the initial review of drm/i915: Separate cherryview from valleyview. In this case, in i915_gem_alloc_context_obj() only call i915_gem_object_set_cache_level() for Ivy Bridge devices since later platforms don't have L3 control bits in the PTE. Cc: Ville Syrjälä C