Re: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values are always valid

2021-10-18 Thread Ville Syrjälä
On Mon, Oct 18, 2021 at 06:13:19PM +0300, Imre Deak wrote: > On Mon, Oct 18, 2021 at 06:04:18PM +0300, Ville Syrjälä wrote: > > On Mon, Oct 18, 2021 at 12:41:52PM +0300, Imre Deak wrote: > > > Print an error if the DPCD sink max lane count is invalid and fix it up. > > > > > > While at it also add

Re: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values are always valid

2021-10-18 Thread Imre Deak
On Mon, Oct 18, 2021 at 06:04:18PM +0300, Ville Syrjälä wrote: > On Mon, Oct 18, 2021 at 12:41:52PM +0300, Imre Deak wrote: > > Print an error if the DPCD sink max lane count is invalid and fix it up. > > > > While at it also add an assert that the link max lane count (derived > > from intel_dp_ma

Re: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values are always valid

2021-10-18 Thread Ville Syrjälä
On Mon, Oct 18, 2021 at 12:41:52PM +0300, Imre Deak wrote: > Print an error if the DPCD sink max lane count is invalid and fix it up. > > While at it also add an assert that the link max lane count (derived > from intel_dp_max_common_lane_count(), potentially reduced by the LT > fallback logic) va

[Intel-gfx] [PATCH 4/6] drm/i915/dp: Ensure sink/link max lane count values are always valid

2021-10-18 Thread Imre Deak
Print an error if the DPCD sink max lane count is invalid and fix it up. While at it also add an assert that the link max lane count (derived from intel_dp_max_common_lane_count(), potentially reduced by the LT fallback logic) value is also valid. Cc: Ville Syrjälä Signed-off-by: Imre Deak ---