Re: [Intel-gfx] [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

2017-05-17 Thread Manasi Navare
On Thu, Apr 06, 2017 at 12:15:36PM -0700, Rodrigo Vivi wrote: > From: Clint Taylor > > vswing programming sequence step 2 requires the Loadgen_select bit to > be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and > lane width. Implemented the change

Re: [Intel-gfx] [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

2017-04-24 Thread Ville Syrjälä
On Thu, Apr 06, 2017 at 12:15:36PM -0700, Rodrigo Vivi wrote: > From: Clint Taylor > > vswing programming sequence step 2 requires the Loadgen_select bit to > be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and > lane width. Implemented the change

[Intel-gfx] [PATCH 40/67] drm/i915/cnl: Enable loadgen_select bit for vswing sequence

2017-04-06 Thread Rodrigo Vivi
From: Clint Taylor vswing programming sequence step 2 requires the Loadgen_select bit to be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and lane width. Implemented the change that was marked as FIXME in the driver. v2: (Rodrigo) checkpatch fixes.