Re: [Intel-gfx] [PATCH 5/5] drm/i915: Fix unclaimed register access due to delayed VGA memroy disable

2013-09-13 Thread Ville Syrjälä
On Fri, Sep 13, 2013 at 05:27:59PM -0300, Paulo Zanoni wrote: > 2013/9/12 : > > From: Ville Syrjälä > > > > VGA registers live inside the power well on HSW, so in order to write > > the VGA MSR register we need the power well to be on. > > > > We really must write to the register to properly clea

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Fix unclaimed register access due to delayed VGA memroy disable

2013-09-13 Thread Paulo Zanoni
2013/9/12 : > From: Ville Syrjälä > > VGA registers live inside the power well on HSW, so in order to write > the VGA MSR register we need the power well to be on. > > We really must write to the register to properly clear the > VGA_MSR_MEM_EN enable bit, even if all VGA registers get zeroed when

[Intel-gfx] [PATCH 5/5] drm/i915: Fix unclaimed register access due to delayed VGA memroy disable

2013-09-12 Thread ville . syrjala
From: Ville Syrjälä VGA registers live inside the power well on HSW, so in order to write the VGA MSR register we need the power well to be on. We really must write to the register to properly clear the VGA_MSR_MEM_EN enable bit, even if all VGA registers get zeroed when the power well is down.