Re: [Intel-gfx] [PATCH 5/5] drm/i915: Optimize VLV/CHV display FIFO updates

2017-03-13 Thread Ville Syrjälä
On Fri, Mar 10, 2017 at 12:07:53PM +0200, Ville Syrjälä wrote: > On Thu, Mar 09, 2017 at 09:26:36PM +, Chris Wilson wrote: > > On Thu, Mar 09, 2017 at 05:44:34PM +0200, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > > Use I915_{READ,WRITE}_FW() for updating the

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Optimize VLV/CHV display FIFO updates

2017-03-10 Thread Ville Syrjälä
On Thu, Mar 09, 2017 at 09:26:36PM +, Chris Wilson wrote: > On Thu, Mar 09, 2017 at 05:44:34PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Use I915_{READ,WRITE}_FW() for updating the DSPARB registers on > > VLV/CHV. This is less expesive as we can grab the unco

Re: [Intel-gfx] [PATCH 5/5] drm/i915: Optimize VLV/CHV display FIFO updates

2017-03-09 Thread Chris Wilson
On Thu, Mar 09, 2017 at 05:44:34PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Use I915_{READ,WRITE}_FW() for updating the DSPARB registers on > VLV/CHV. This is less expesive as we can grab the uncore.lock across > the entire sequence of reads and writes instead of each

[Intel-gfx] [PATCH 5/5] drm/i915: Optimize VLV/CHV display FIFO updates

2017-03-09 Thread ville . syrjala
From: Ville Syrjälä Use I915_{READ,WRITE}_FW() for updating the DSPARB registers on VLV/CHV. This is less expesive as we can grab the uncore.lock across the entire sequence of reads and writes instead of each register access grabbing it. This also allows us to eliminate the dsparb lock entirely