Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On 15/05/2023 23:07, Dixit, Ashutosh wrote: On Mon, 15 May 2023 03:10:56 -0700, Tvrtko Ursulin wrote: Hi Tvrtko, On 12/05/2023 21:57, Umesh Nerlige Ramappa wrote: On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: On 12/05/2023 02:08, Dixit, Ashutosh wrote: On Fri, 05

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Mon, 15 May 2023 03:10:56 -0700, Tvrtko Ursulin wrote: > Hi Tvrtko, > On 12/05/2023 21:57, Umesh Nerlige Ramappa wrote: > > On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: > >> > >> On 12/05/2023 02:08, Dixit, Ashutosh wrote: > >>> On Fri, 05 May 2023 17:58:15 -0700, Umesh

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Mon, May 15, 2023 at 11:12:33AM +0100, Tvrtko Ursulin wrote: On 15/05/2023 07:44, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On 15/05/2023 07:44, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On 12/05/2023 21:57, Umesh Nerlige Ramappa wrote: On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: On 12/05/2023 02:08, Dixit, Ashutosh wrote: On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config

[Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, May 12, 2023 at 09:41:56PM -0700, Dixit, Ashutosh wrote: On Fri, 12 May 2023 18:55:44 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, 12 May 2023 18:55:44 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > Reserve some bits in the counter config namespace which will carry the > tile id and prepare the code to handle this. > > No per tile counters have been added yet. > > v2: > - Fix checkpatch issues > -

[Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, 12 May 2023 13:57:59 -0700, Umesh Nerlige Ramappa wrote: > > On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: > > > > On 12/05/2023 02:08, Dixit, Ashutosh wrote: > >> On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: > >>> > >>> From: Tvrtko Ursulin > >>> >

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, May 12, 2023 at 01:57:59PM -0700, Umesh Nerlige Ramappa wrote: On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: On 12/05/2023 02:08, Dixit, Ashutosh wrote: On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, May 12, 2023 at 11:56:18AM +0100, Tvrtko Ursulin wrote: On 12/05/2023 02:08, Dixit, Ashutosh wrote: On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On 12/05/2023 02:08, Dixit, Ashutosh wrote: On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet.

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, 05 May 2023 17:58:15 -0700, Umesh Nerlige Ramappa wrote: > > From: Tvrtko Ursulin > > Reserve some bits in the counter config namespace which will carry the > tile id and prepare the code to handle this. > > No per tile counters have been added yet. > > v2: > - Fix checkpatch issues > -

Re: [Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

On Fri, May 05, 2023 at 05:58:15PM -0700, Umesh Nerlige Ramappa wrote: From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits

[Intel-gfx] [PATCH 5/6] drm/i915/pmu: Prepare for multi-tile non-engine counters

From: Tvrtko Ursulin Reserve some bits in the counter config namespace which will carry the tile id and prepare the code to handle this. No per tile counters have been added yet. v2: - Fix checkpatch issues - Use 4 bits for gt id in non-engine counters. Drop FIXME. - Set MAX GTs to 4. Drop