On Mon, Mar 20, 2023 at 01:51:54PM +0200, Imre Deak wrote:
> On Mon, Mar 20, 2023 at 11:54:37AM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> > [...]
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index
On Mon, Mar 20, 2023 at 11:54:37AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
> [...]
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index f86060195987..f2c9f88e7aef 100644
> ---
From: Ville Syrjälä
Keeping DC states enabled is incompatible with the _noarm()/_arm()
split we use for writing pipe/plane registers. When DC5 and PSR
are enabled, all pipe/plane registers effectively become self-arming
on account of DC5 exit arming the update, and PSR exit latching it.
What
