Re: [Intel-gfx] [PATCH 5/9] drm/i915: drop unnecessary clearing of pch dp transcoder timings

2012-11-16 Thread Daniel Vetter
On Fri, Nov 16, 2012 at 8:52 PM, Paulo Zanoni wrote: > Notice that we have the CPU M/N registers and the PCH M/N registers. > And the PCH M/N registers are only used by DisplayPort, so it makes > sense to zero them for non-DisplayPort. If we really want this, how > about we add this patch only in

Re: [Intel-gfx] [PATCH 5/9] drm/i915: drop unnecessary clearing of pch dp transcoder timings

2012-11-16 Thread Paulo Zanoni
Hi 2012/11/5 Daniel Vetter : > This has originally been added in > > commit 8db9d77b1b14fd730561f64beea8c00e4478d7c5 > Author: Zhenyu Wang > Date: Wed Apr 7 16:15:54 2010 +0800 > > drm/i915: Support for Cougarpoint PCH display pipeline > > probably to combat issues with hw state left behind

[Intel-gfx] [PATCH 5/9] drm/i915: drop unnecessary clearing of pch dp transcoder timings

2012-11-05 Thread Daniel Vetter
This has originally been added in commit 8db9d77b1b14fd730561f64beea8c00e4478d7c5 Author: Zhenyu Wang Date: Wed Apr 7 16:15:54 2010 +0800 drm/i915: Support for Cougarpoint PCH display pipeline probably to combat issues with hw state left behind by the BIOS. And indeed, I've checked out th