Re: [Intel-gfx] [PATCH 5/9] drm/i915: pnv dpll doesn't use m1!

2013-06-12 Thread Daniel Vetter
On Wed, Jun 12, 2013 at 12:38:40AM +0100, Damien Lespiau wrote: > On Tue, May 21, 2013 at 09:54:55PM +0200, Daniel Vetter wrote: > > So don't try to store it in the DPLL_FP register. > > > > Otherwise it looks like the limits for pineview are correct: It has > > it's own clock computation code, wh

Re: [Intel-gfx] [PATCH 5/9] drm/i915: pnv dpll doesn't use m1!

2013-06-11 Thread Damien Lespiau
On Tue, May 21, 2013 at 09:54:55PM +0200, Daniel Vetter wrote: > So don't try to store it in the DPLL_FP register. > > Otherwise it looks like the limits for pineview are correct: It has > it's own clock computation code, which doesn't use an offset for n > divisors, and the register value based m

[Intel-gfx] [PATCH 5/9] drm/i915: pnv dpll doesn't use m1!

2013-05-21 Thread Daniel Vetter
So don't try to store it in the DPLL_FP register. Otherwise it looks like the limits for pineview are correct: It has it's own clock computation code, which doesn't use an offset for n divisors, and the register value based m limits look sane enough. v2: Rebase on top of the pineview clock refact