Re: [Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management

2021-07-22 Thread Matthew Brost
On Thu, Jul 22, 2021 at 02:50:24PM -0700, Daniele Ceraolo Spurio wrote: > > > > > > > @@ -1756,15 +1796,119 @@ static int guc_context_alloc(struct > > > > intel_context *ce) > > > > return lrc_alloc(ce, ce->engine); > > > >} > > > > +static void guc_context_set_prio(struct intel_guc

Re: [Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management

2021-07-22 Thread Daniele Ceraolo Spurio
@@ -1756,15 +1796,119 @@ static int guc_context_alloc(struct intel_context *ce) return lrc_alloc(ce, ce->engine); } +static void guc_context_set_prio(struct intel_guc *guc, +struct intel_context *ce, +u8 prio) +{ +

Re: [Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management

2021-07-22 Thread Matthew Brost
On Thu, Jul 22, 2021 at 01:26:30PM -0700, Daniele Ceraolo Spurio wrote: > > > On 7/16/2021 1:17 PM, Matthew Brost wrote: > > Implement a simple static mapping algorithm of the i915 priority levels > > (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as > > follows: > > > > i915 l

Re: [Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management

2021-07-22 Thread Daniele Ceraolo Spurio
On 7/16/2021 1:17 PM, Matthew Brost wrote: Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i91

[Intel-gfx] [PATCH 50/51] drm/i915/guc: Implement GuC priority management

2021-07-16 Thread Matthew Brost
Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i915 level < INT_MAX-> GuC high level(1) i9