Re: [Intel-gfx] [PATCH 6/7] drm/i915: Use Engine1 instance for gen11 pm interrupts

2019-04-10 Thread Chris Wilson
Quoting Mika Kuoppala (2019-04-10 11:59:22) > With gen11 the interrupt registers are shared between 2 engines, > with Engine1 instance being upper word and Engine0 instance being > lower. Annoyingly gen11 selected the pm interrupts to be in the > Engine1 instance. > > Rectify the situation by

[Intel-gfx] [PATCH 6/7] drm/i915: Use Engine1 instance for gen11 pm interrupts

2019-04-10 Thread Mika Kuoppala
With gen11 the interrupt registers are shared between 2 engines, with Engine1 instance being upper word and Engine0 instance being lower. Annoyingly gen11 selected the pm interrupts to be in the Engine1 instance. Rectify the situation by shifting the access accordingly, based on gen. v2: