Re: [Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

2012-10-25 Thread Jesse Barnes
On Tue, 23 Oct 2012 12:42:07 +0100 Chris Wilson ch...@chris-wilson.co.uk wrote: On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes jbar...@virtuousgeek.org wrote: If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush

[Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

2012-10-25 Thread Jesse Barnes
If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set. So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org ---

Re: [Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

2012-10-23 Thread Chris Wilson
On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes jbar...@virtuousgeek.org wrote: If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set. That quotation doesn't make sense

[Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

2012-10-18 Thread Jesse Barnes
If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set. So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org ---

[Intel-gfx] [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall

2012-10-18 Thread Jesse Barnes
If ENABLED, PIPE_CONTROL command will flush the in flight data written out by render engine to Global Observation point on flush done. Also Requires stall bit ([20] of DW1) set. So set the stall bit to ensure proper invalidation. Signed-off-by: Jesse Barnes jbar...@virtuousgeek.org ---