On Fri, Oct 20, 2017 at 09:44:53PM +, Runyan, Arthur J wrote:
> If you know which direction voltage is moving, then you can optimize. Nobody
> snooping PLL. Really only the DVFS post sequence is needed, placed either
> before or after the clock programming, depending on whether voltage is
On Fri, Oct 20, 2017 at 01:36:42PM -0700, Rodrigo Vivi wrote:
> On Fri, Oct 20, 2017 at 08:07:07PM +, Ville Syrjälä wrote:
> > On Fri, Oct 20, 2017 at 05:48:54PM +, Runyan, Arthur J wrote:
> > > Sorry about top reply from corporate email...
> > > If you know in advance that you will just be
If you know which direction voltage is moving, then you can optimize. Nobody
snooping PLL. Really only the DVFS post sequence is needed, placed either
before or after the clock programming, depending on whether voltage is
increasing or decreasing. But you shouldn't optimize that far since nob
On Fri, Oct 20, 2017 at 08:07:07PM +, Ville Syrjälä wrote:
> On Fri, Oct 20, 2017 at 05:48:54PM +, Runyan, Arthur J wrote:
> > Sorry about top reply from corporate email...
> > If you know in advance that you will just be temporarily disabling the PLL,
> > then your sequence works.
>
> A
On Fri, Oct 20, 2017 at 05:48:54PM +, Runyan, Arthur J wrote:
> Sorry about top reply from corporate email...
> If you know in advance that you will just be temporarily disabling the PLL,
> then your sequence works.
Actually we would end up using this sequence even if disable the PLL for
goo
Sorry about top reply from corporate email...
If you know in advance that you will just be temporarily disabling the PLL,
then your sequence works.
-Original Message-
From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
Sent: Friday, 20 October, 2017 4:12 AM
To: Vivi, Rodrigo
Cc:
On Fri, Oct 20, 2017 at 05:18:04PM +0300, Ville Syrjälä wrote:
> On Thu, Oct 19, 2017 at 04:54:56PM -0700, Rodrigo Vivi wrote:
> >
> > On Wed, Oct 18, 2017 at 08:48:25PM +, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > On CNL we may need to bump up the system agent voltage not o
On Thu, Oct 19, 2017 at 04:54:56PM -0700, Rodrigo Vivi wrote:
>
> On Wed, Oct 18, 2017 at 08:48:25PM +, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On CNL we may need to bump up the system agent voltage not only due
> > to CDCLK but also when driving DDI port with a sufficiently hig
On Thu, Oct 19, 2017 at 04:54:56PM -0700, Rodrigo Vivi wrote:
>
> On Wed, Oct 18, 2017 at 08:48:25PM +, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > On CNL we may need to bump up the system agent voltage not only due
> > to CDCLK but also when driving DDI port with a sufficiently hig
On Wed, Oct 18, 2017 at 08:48:25PM +, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On CNL we may need to bump up the system agent voltage not only due
> to CDCLK but also when driving DDI port with a sufficiently high clock.
> To that end start tracking the minimum acceptable voltage for e
From: Ville Syrjälä
On CNL we may need to bump up the system agent voltage not only due
to CDCLK but also when driving DDI port with a sufficiently high clock.
To that end start tracking the minimum acceptable voltage for each crtc.
We do the tracking via crtcs because we don't have any kind of e
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