Re: [Intel-gfx] [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit register on Haswell

2013-05-20 Thread Ville Syrjälä
On Fri, May 03, 2013 at 05:23:44PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > And the SNB_READ_WM0_LATENCY macro is not valid anymore because we > have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if > the new one is not zero. > > Signed-off-by: Paulo Zanoni Reviewed-b

[Intel-gfx] [PATCH 8/9] drm/i915: MCH_SSKPD is a 64 bit register on Haswell

2013-05-03 Thread Paulo Zanoni
From: Paulo Zanoni And the SNB_READ_WM0_LATENCY macro is not valid anymore because we have the "New WM0" at 63:56, so the "Old WM0" could maybe be zero if the new one is not zero. Signed-off-by: Paulo Zanoni --- drivers/gpu/drm/i915/intel_pm.c |2 +- 1 file changed, 1 insertion(+), 1 delet