On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
inside haswell_init_clock_gating and mentioned it is a workaround for
early silicon revisions and should be removed
2013/5/21 Daniel Vetter dan...@ffwll.ch:
On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
inside haswell_init_clock_gating and mentioned it is a workaround for
early
On Fri, May 03, 2013 at 05:23:45PM -0300, Paulo Zanoni wrote:
From: Paulo Zanoni paulo.r.zan...@intel.com
Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
inside haswell_init_clock_gating and mentioned it is a workaround for
early silicon revisions and should be removed
From: Paulo Zanoni paulo.r.zan...@intel.com
Commit 1544d9d57396d5c0c6b7644ed5ae1f4d6caad07a added a workaround
inside haswell_init_clock_gating and mentioned it is a workaround for
early silicon revisions and should be removed later. This workaround
is documented in bit 31 of PRI_CTL. I asked