Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: Limit clflush to active cachelines

2017-03-10 Thread Chris Wilson
On Fri, Mar 10, 2017 at 01:19:01PM +0200, Mika Kuoppala wrote: > Chris Wilson writes: > > > We only need to clflush those cachelines that we have validated to be > > read by the GPU. Userspace typically fills the batch length in > > correctly, the exceptions tend to be explicit tests within igt.

Re: [Intel-gfx] [PATCH v2] drm/i915/cmdparser: Limit clflush to active cachelines

2017-03-10 Thread Mika Kuoppala
Chris Wilson writes: > We only need to clflush those cachelines that we have validated to be > read by the GPU. Userspace typically fills the batch length in > correctly, the exceptions tend to be explicit tests within igt. > > v2: Use ptr_mask_bits() to make Mika happy > > Signed-off-by: Chris W

[Intel-gfx] [PATCH v2] drm/i915/cmdparser: Limit clflush to active cachelines

2017-03-10 Thread Chris Wilson
We only need to clflush those cachelines that we have validated to be read by the GPU. Userspace typically fills the batch length in correctly, the exceptions tend to be explicit tests within igt. v2: Use ptr_mask_bits() to make Mika happy Signed-off-by: Chris Wilson Cc: Mika Kuoppala --- driv