The Bspec:49291 is now changed to reflect that for all platforms the
DCC_MODE will be programmed to DCC_MODE_SELECT_ONCE,
rather than DCC_MODE_SELECT_CONTINUOUSLY.
I will send new patch for the same.
Regards,
Ankit
On 8/10/2022 8:26 PM, Ankit Nautiyal wrote:
Wa_22012718247 : When Display PH
Wa_22012718247 : When Display PHY is configured in continuous
DCC calibration mode, the DCC (duty cycle correction) for the clock
erroneously goes through a state where the DCC code is 0x00 when it is
supposed to be transitioning from 0x10 to 0x0F. This glitch causes a
distortion in the clock, whic
