Re: [Intel-gfx] [PATCH v2] drm/i915: Reading DPRX caps in LTTPR transparent mode after LTTPR detection

2021-05-28 Thread Almahallawy, Khaled
On Sat, 2021-05-29 at 13:17 +0800, William Tseng wrote: > In some cases, the MAX_LANE_COUNT in the register at DCPD Address > 0002h > may be updated by LTTPR in non-transparent mode while reading DPRX > Caps > registers, e.g., the lane count is changed from 2 to 4. This may > cause > Link Training

[Intel-gfx] [PATCH v2] drm/i915: Reading DPRX caps in LTTPR transparent mode after LTTPR detection

2021-05-28 Thread William Tseng
In some cases, the MAX_LANE_COUNT in the register at DCPD Address 0002h may be updated by LTTPR in non-transparent mode while reading DPRX Caps registers, e.g., the lane count is changed from 2 to 4. This may cause Link Training failure because of the updated lane count, which might not be supporte