From: Tvrtko Ursulin <tvrtko.ursu...@intel.com> A few bugs in programming the MCR register sneaked in past code review.
First of all fls() usage is wrong and suffers from off-by-one problem. Secondly the assert in WaProgramMgsrForL3BankSpecificMmioReads is also wrong due inverted logic. With MCR programming fixed we can stop ignoring the engine workarounds verification of GEN8_L3SQCREG4. But not registers in the 0xb100-0xb3ff range which cannot be read reliably by the command streamers. The logic is also improved to not only assert when static MCR configuration would not work given specific subslice and L3 bank configuration, but to find a valid static configuration if possible. Finally there was a missing perfomance based workaround which loosely belongs to this overall story of ICL, subslices, L3 banks and workarounds. Tvrtko Ursulin (6): drm/i915: Fix GEN8_MCR_SELECTOR programming drm/i915: Trust programmed MCR in read_subslice_reg drm/i915: Fix and improve MCR selection logic drm/i915: Skip CS verification of L3 bank registers drm/i915/icl: Verify engine workarounds in GEN8_L3SQCREG4 drm/i915/icl: Add Wa_1409178092 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 56 ++----- drivers/gpu/drm/i915/gt/intel_workarounds.c | 161 ++++++++++++-------- drivers/gpu/drm/i915/i915_drv.h | 2 - drivers/gpu/drm/i915/i915_reg.h | 3 + 4 files changed, 109 insertions(+), 113 deletions(-) -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
