Re: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs

2020-05-07 Thread Ville Syrjälä
On Mon, May 04, 2020 at 03:52:17PM -0700, Matt Roper wrote: > When Rocket Lake is paired with a TGP PCH, the last two outputs utilize > the TC1 and TC2 hpd pins, even though these are combo outputs. > > Bspec: 49181 > Cc: Lucas De Marchi > Signed-off-by: Matt Roper > --- > drivers/gpu/drm/i915/

Re: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs

2020-05-07 Thread Srivatsa, Anusha
> -Original Message- > From: Intel-gfx On Behalf Of Matt > Roper > Sent: Tuesday, May 5, 2020 4:22 AM > To: intel-gfx@lists.freedesktop.org > Cc: De Marchi, Lucas > Subject: [Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits > for > TC

[Intel-gfx] [PATCH v2 12/22] drm/i915/rkl: Check proper SDEISR bits for TC1 and TC2 outputs

2020-05-04 Thread Matt Roper
When Rocket Lake is paired with a TGP PCH, the last two outputs utilize the TC1 and TC2 hpd pins, even though these are combo outputs. Bspec: 49181 Cc: Lucas De Marchi Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletion