Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Add PSR2 selective update status registers and bits definitions

2019-01-10 Thread Souza, Jose
On Wed, 2019-01-09 at 18:18 -0800, Dhinakaran Pandiyan wrote: > On Thu, 2019-01-03 at 06:21 -0800, José Roberto de Souza wrote: > > This register contains how many blocks was sent in the past > > selective > > updates. > > Those registers are not kept set all the times but pulling it > > after > I

Re: [Intel-gfx] [PATCH v2 5/6] drm/i915: Add PSR2 selective update status registers and bits definitions

2019-01-09 Thread Dhinakaran Pandiyan
On Thu, 2019-01-03 at 06:21 -0800, José Roberto de Souza wrote: > This register contains how many blocks was sent in the past selective > updates. > Those registers are not kept set all the times but pulling it after I suppose you mean 'polling'. > flip > can show that the expected values are set

[Intel-gfx] [PATCH v2 5/6] drm/i915: Add PSR2 selective update status registers and bits definitions

2019-01-03 Thread José Roberto de Souza
This register contains how many blocks was sent in the past selective updates. Those registers are not kept set all the times but pulling it after flip can show that the expected values are set for the current frame and the previous ones too. v2: Improved macros(Dhinakaran) Cc: Rodrigo Vivi Cc: